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DRA722_17 Datasheet, PDF (264/408 Pages) Texas Instruments – Infotainment Applications Processor
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 7-46. Timing Requirements for McASP1(1)
NO.
1
2
3
4
PARAMETER
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
DESCRIPTION
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
MODE
MIN
20
0.35P (2)
20
0.5R - 3
(3)
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
7
tsu(AXR-ACLK)
Setup time, AXR input valid before ACLKR/X
8
th(ACLK-AXR)
Hold time, AXR input valid after ACLKR/X
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
ACLKR/X int 20.5
ACLKR/X ext
4
in
ACLKR/X ext
out
ACLKR/X int
-1
ACLKR/X ext
1.7
in
ACLKR/X ext
out
ACLKR/X int 21.6
ACLKR/X ext 11.5
in
ACLKR/X ext
out
ACLKR/X int
-1
ACLKR/X ext
1.8
in
ACLKR/X ext
out
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 7-47. Timing Requirements for McASP2(1)
NO. PARAMETER DESCRIPTION
1
tc(AHCLKRX)
2
tw(AHCLKRX)
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
MODE
MIN
20
0.35P
(2)
MAX
3
tc(ACLKRX)
Cycle time, ACLKR/X
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
Any Other Conditions
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M"
Virtual IO Timing Modes
Any Other Conditions
20
12.5
0.5R - 3
(3)
5
tsu(AFSRX-ACLK) Setup time, AFSR/X input valid before
ACLKR/X
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M"
Virtual IO Timing Modes
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
0.38R
(3)
20.3
4.5
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
264 Timing Requirements and Switching Characteristics
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