DRA722_17 Datasheet, PDF (265/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-47. Timing Requirements for McASP2⁽¹⁾ (continued)
NO. PARAMETER DESCRIPTION
MODE
MIN
6 t_{h(ACLK-AFSRX)} Hold time, AFSR/X input valid after ACLKR/X
ACLKR/X int
-1
ACLKR/X ext in
1.8
ACLKR/X ext out
ACLKR/X ext in
3
ACLKR/X ext out "80M" Virtual
IO Timing Modes
7
t_su(AXR-ACLK)
Setup time, AXR input valid before ACLKR/X
ACLKR/X int
21.1
ACLKR/X ext in
4.5
ACLKR/X ext out
ACLKR/X ext in
3
ACLKR/X ext out "80M" Virtual
IO Timing Modes
8
t_h(ACLK-AXR)
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
-1
ACLKR/X ext in
1.8
ACLKR/X ext out
ACLKR/X ext in
3
ACLKR/X ext out "80M" Virtual
IO Timing Modes
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 7-48. Timing Requirements for McASP3/4/5/6/7/8⁽¹⁾
NO.
1
2
PARAMETER
t_c(AHCLKRX)
t_w(AHCLKRX)
DESCRIPTION
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
MODE
MIN
20
0.35P
(2)
MAX
UNIT
ns
ns
3
t_c(ACLKRX)
4
t_w(ACLKRX)
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
20
ns
0.5R - 3
ns
(3)
5
t_{su(AFSRX-ACLK)}
Setup time, AFSR/X input valid before ACLKR/X
ACLKR/X int
19.7
ns
ACLKR/X ext in 5.6
ns
ACLKR/X ext out
6
t_{h(ACLK-AFSRX)}
Hold time, AFSR/X input valid after ACLKR/X
ACLKR/X int
-1.1
ns
ACLKR/X ext in 2.5
ns
ACLKR/X ext out
t_su(AXR-ACLK)
Setup time, AXR input valid before ACLKX
ACLKX int
20.3
ns
(ASYNC=0)
ACLKR/X ext in 5.1
ns
ACLKR/X ext out
8
t_h(ACLK-AXR)
Hold time, AXR input valid after ACLKX
ACLKX int
-0.8
ns
(ASYNC=0)
ACLKR/X ext in 2.5
ns
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
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Timing Requirements and Switching Characteristics 265
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