DRA722_17 Datasheet, PDF (17/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
BALL NUMBER
[1]
BALL NAME [2]
AH25
ddr1_dqs0
AE27
ddr1_dqs1
AD27
ddr1_dqs2
Y28
ddr1_dqs3
AG25
ddr1_dqsn0
AE28
ddr1_dqsn1
AD28
ddr1_dqsn2
Y27
ddr1_dqsn3
V28
ddr1_dqsn_ecc
V27
ddr1_dqs_ecc
W22
ddr1_ecc_d0
V23
ddr1_ecc_d1
W19
ddr1_ecc_d2
W23
ddr1_ecc_d3
Y25
ddr1_ecc_d4
V24
ddr1_ecc_d5
V25
ddr1_ecc_d6
Y26
ddr1_ecc_d7
AH24
ddr1_nck
AE20
ddr1_odt0
AC17
ddr1_odt1
AF20
ddr1_rasn
AG21
ddr1_rst
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
SIGNAL NAME [3]
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_dqsn_ecc
ddr1_dqs_ecc
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_nck
ddr1_odt0
ddr1_odt1
ddr1_rasn
ddr1_rst
Table 4-2. Ball Characteristics⁽¹⁾ (continued)
MUXMODE
[4]
TYPE [5]
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
O
0
O
0
O
0
O
0
O
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
BALL
RESET REL.
MUXMODE
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
PD
PD
1.35/1.5
vdds_ddr1 NA
PD
PD
1.35/1.5
vdds_ddr1 NA
PD
PD
1.35/1.5
vdds_ddr1 NA
PD
PD
1.35/1.5
vdds_ddr1 NA
PU
PU
1.35/1.5
vdds_ddr1 NA
PU
PU
1.35/1.5
vdds_ddr1 NA
PU
PU
1.35/1.5
vdds_ddr1 NA
PU
PU
1.35/1.5
vdds_ddr1 NA
PU
PU
1.35/1.5
vdds_ddr1 NA
PD
PD
1.35/1.5
vdds_ddr1 NA
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1 No
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1 No
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
DSIS [14]
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726
Terminal Configuration and Functions
17