DRA722_17 Datasheet, PDF (146/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Instance Name Input Clock Name
SMARTREFLEX_C
ORE
MCLK
SYSCLK
SMARTREFLEX_D
SP
MCLK
SYSCLK
SMARTREFLEX_G
PU
MCLK
SYSCLK
SMARTREFLEX_IV
AHD
MCLK
SYSCLK
SMARTREFLEX_M
PU
MCLK
SYSCLK
SPINLOCK
TIMER1
SPINLOCK_ICLK
TIMER1_ICLK
TIMER1_FCLK
Clock
Type
Int
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int
Int
Func
Max. Clock
Allowed (MHz)
133
38.4
133
38.4
133
38.4
133
38.4
133
38.4
266
38.4
100
PRCM Clock Name
COREAON_L4_GICLK
WKUPAON_ICLK
COREAON_L4_GICLK
WKUPAON_ICLK
COREAON_L4_GICLK
WKUPAON_ICLK
COREAON_L4_GICLK
WKUPAON_ICLK
COREAON_L4_GICLK
WKUPAON_ICLK
L4CFG_L3_GICLK
WKUPAON_GICLK
TIMER1_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
PLL / OSC /
Source Name
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
OSC1
OSC1
RTC Oscillator
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
146 Specifications
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