DRA722_17 Datasheet, PDF (308/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-109 Virtual
Functions Mapping for MMC1 for a definition of the Virtual modes.
Table 7-109 presents the values for DELAYMODE bitfield.
BALL
W6
Y6
AA6
Y4
AA5
Y3
Table 7-109. Virtual Functions Mapping for MMC1
BALL NAME
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
MMC1_
VIRTUAL1
15
15
15
15
15
15
Delay Mode Value
MMC1_
VIRTUAL4
MMC1_
VIRTUAL5
12
11
12
11
12
11
12
11
12
11
12
11
MMC1_
VIRTUAL6
10
10
10
10
10
10
MUXMODE
0
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-110 Manual
Functions Mapping for MMC1 for a definition of the Manual modes.
Table 7-110 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
308 Timing Requirements and Switching Characteristics
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726