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| DRA722_17 Datasheet, PDF (248/408 Pages) Texas Instruments – Infotainment Applications Processor | |||
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DRA722, DRA724, DRA725, DRA726
SPRS956B â MARCH 2016 â REVISED JANUARY 2017
www.ti.com
Table 7-32. Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)(1) (continued)
NO. PARAMETER
7
th(SCLL-SDAV)
DESCRIPTION
Hold time, SDA valid after SCL
low
Cb = 100 pF MAX
MIN
MAX
0 (3)
70
Cb = 400 pF (2)
MIN
MAX
0 (3)
150
UNIT
ns
13
tsu(SCLH-SDAH)
Setup time, SCL high before
160
SDA high (for a STOP condition)
160
ns
14 tw(SP)
15
Cb (2)
Pulse duration, spike (must be
0
10
0
10
ns
suppressed)
Capacitive load for SDAH and
100
SCLH lines
400
pF
16 Cb
Capacitive load for SDAH + SDA
400
line and SCLH + SCL line
(1) I2C HS-Mode is only supported on I2C3/4/5/6. I2C HS-Mode is not supported on I2C1/2.
400
pF
(2) For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
I2Ci_SDA
I2Ci_SCL
11
8
4
10
1
7
3
6
5
12
3
2
9
14
13
Stop Start
Repeated
Start
Stop
Figure 7-23. I2C Receive Timing
SPRS906_TIMING_I2C_01
Table 7-33 and Figure 7-24 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 7-33. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)
NO. PARAMETER
DESCRIPTION
16 tc(SCL)
17 tsu(SCLH-SDAL)
18 th(SDAL-SCLL)
19 tw(SCLL)
20 tw(SCLH)
21 tsu(SDAV-SCLH)
22 th(SCLL-SDAV)
23 tw(SDAH)
Cycle time, SCL
Setup time, SCL high before SDA low (for a
repeated START condition)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (for I2C
bus devices)
Pulse duration, SDA high between STOP and
START conditions
STANDARD MODE
MIN
MAX
10
4.7
4
4.7
4
250
0
3.45
4.7
FAST MODE
MIN
MAX
2.5
0.6
0.6
1.3
0.6
100
0
0.9
1.3
UNIT
µs
µs
µs
µs
µs
ns
µs
µs
248 Timing Requirements and Switching Characteristics
Copyright © 2016â2017, Texas Instruments Incorporated
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Product Folder Links: DRA722 DRA724 DRA725 DRA726
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