DRA722_17 Datasheet, PDF (389/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Rtt
A2
A3
A4
A3
AT
Vtt
=
SPRS906_PCB_DDR3_11
Figure 8-50. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
8.7.2.15.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
8.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 8-51 shows the topology of the CK net classes and Figure 8-52 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR Differential CK Input Buffers
+–
+–
Processor
+
Differential Clock
Output Buffer
–
Clock Parallel
Terminator
Rcp
DDR_1V5
A1
A2
A3
AT
Cac
Rcp
0.1 µF
A1
A2
A3
AT
Routed as Differential Pair
Figure 8-51. CK Topology for Two DDR3 Devices
SPRS906_PCB_DDR3_12
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Applications, Implementation, and Layout 389
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