DRA722_17 Datasheet, PDF (269/408 Pages) Texas Instruments – Infotainment Applications Processor

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9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
11
ACLKR/X (CLKRP = CLKXP = 1) ^(A)
ACLKR/X (CLKRP = CLKXP = 0) ^(B)
AFSR/X (Bit Width, 0 Bit Delay)
10
10
12
12
13
13
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
13
13
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
13
AFSR/X (Slot Width, 0 Bit Delay)
13
13
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
14
15
AXR[n] (Data Out/T ransmit)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_02
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 7-42. McASP Output Timing
Table 7-52 through Table 7-59 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see
Figure 7-43 through Figure 7-50).
No. CASE
1 COIFOI
Table 7-52. Virtual Mode Case Details for McASP1
CASE Description
CLKX / FSX: Output
CLKR / FSR: Input
Virtual Mode Settings
Signals
Virtual Mode Value
IP Mode : ASYNC
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP1_VIRTUAL2_ASYNC_RX
Notes
See Figure 7-43
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Timing Requirements and Switching Characteristics 269
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