DRA722_17 Datasheet, PDF (371/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
8.5.6 PCIe Board Design and Layout Guidelines
The PCIe interface on the device provides support for a 5.0 Gbps lane with polarity inversion.
8.5.6.1 PCIe Connections and Interface Compliance
The PCIe interface on the device is compliant with the PCIe revision 2.0 specification. Please refer to the
PCIe specifications for all connections that are described in it. Those recommendations are more
descriptive and exhaustive than what is possible here.
The use of PCIe compatible bridges and switches is allowed for interfacing with more than one other
processor or PCIe device.
8.5.6.1.1 Coupling Capacitors
AC coupling capacitors are required on the transmit data pair. Table 8-21 shows the requirements for
these capacitors.
Table 8-21. PCIe AC Coupling Capacitors Requirements
PARAMETER
MIN
TYP
MAX
UNIT
PCIe AC coupling capacitor value
PCIe AC coupling capacitor package size
90
100
110
nF
0402
0603
EIA⁽¹⁾⁽²⁾
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
8.5.6.1.2 Polarity Inversion
The PCIe specification requires polarity inversion support. This means for layout purposes, polarity is
unimportant because each signal can change its polarity on die inside the chip. This means polarity within
a lane is unimportant for layout.
8.5.6.2 Non-standard PCIe connections
The following sections contain suggestions for any PCIe connection that is NOT described in the official
PCIe specification, such as an on-board Device to Device or Device to other PCIe compliant processor
connection.
8.5.6.2.1 PCB Stackup Specifications
Table 8-22 shows the stackup and feature sizes required for these types of PCIe connections.
Table 8-22. PCIe PCB Stackup Specifications
PARAMETER
MIN
TYP
Number of ground plane cuts allowed within PCIe routing
region
-
-
Number of layers between PCIe routing area and reference
plane ⁽¹⁾
-
-
PCB Routing clearance
4
PCB Trace width
4
MAX
0
0
UNIT
Cuts
Layers
Mils
Mils
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Applications, Implementation, and Layout 371
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