DRA722_17 Datasheet, PDF (347/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 8-5. TPS65917 Power Supply
Connections (continued)
TPS65917
SMPS2 ⁽²⁾
SMPS3 ⁽²⁾
SMPS4 ⁽³⁾
SMPS5 ⁽⁴⁾
Valid
Combination
1:
vdd_dsp,
vdd_gpu,
vdd_iva
vdd
vdds18v
vdds_ddr1
Valid
Combination 2:
vdd
vdd_dspeve,
vdd_gpu,
vdd_iva
vdds18v
vdds_ddr1
TPS65917
Current Rating
Limitation ^{(1) (3)}
3.5A
3A
1.5A
2A
(1) Refer to the TPS65917 Data Manual for exact current rating limitations, including assumed V_IN and other parameters. Values provided in
this table are for comparison purposes.
(2) DSP, EVE, GPU, and IVAHD power consumption is highly application-specific. Separate analysis must be performed to ensure output
current ratings (average and peak) is within the limits of the PMIC. VDD only supports OPP_NOM.
(3) Highly application-specific. Separate analysis must be performed to ensure average and peak power is within the limits of the PMIC.
(4) Furthermore, if SMPS5 is used for DDR power, both total memory + SoC power must be within the PMIC limits.
8.3.6 DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65917 PMIC LDOLN output is specifically designed to meet this low noise requirement.
NOTE
For more information about Input Voltage Sources, see Section 6.2 DPLLs, DLLs
Specifications.
Table 8-4 presents the voltage inputs that supply the DPLLs.
Table 8-6. Input Voltage Power Supplies for the DPLLs
POWER SUPPLY
vdda_per
vdda_ddr
vdda_debug
vdda_dsp_iva
vdda_core_gmac
vdda_gpu
vdda_video
vdda_mpu_abe
vdda_osc
vdda_pll_spare
DPLLs
DPLL_PER and PER HSDIVIDER analog power supply
DPLL_DDR and DDR HSDIVIDER analog power supply
DPLL_DEBUG analog power supply
DPLL_DSP and DPLL_IVA analog power supply
DPLL_CORE and HSDIVIDER analog power supply
DPLL_GPU analog power supply
DPLL_VIDEO1 analog power supply
DPLL_MPU and DPLL_ABE analog power supply
not DPLL input but is required to be supplied by low noise input voltage
DPLL_SPARE analog power supply
8.3.7 Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the
vdd_mpu key processor power domain.
NOTE
Materials presented in this section are based on generic PDN analysis on PCB boards and
are not specific to systems integrating the Device.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 347
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