DRA722_17 Datasheet, PDF (11/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
9. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).
10. POWER: The voltage supply that powers the terminal IO buffers.
11. HYS: Indicates if the input buffer is with hysteresis:
– Yes: With hysteresis
– No: Without hysteresis
An empty box means "Yes".
NOTE
For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.
12. BUFFER TYPE: Drive strength of the associated output buffer.
NOTE
For programmable buffer strength:
– The default value is given in Table 4-2.
– A note describes all possible values according to the selected muxmode.
13. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or
logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
– 0: Logic 0 driven on the peripheral's input signal port.
– 1: Logic 1 driven on the peripheral's input signal port.
– blank: Pin state driven on the peripheral's input signal port.
NOTE
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration (Hi-Z mode is not
an input signal).
NOTE
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
NOTE
Some of the EMIF1 signals have an additional state change at the release of porz. The state
that the signals change to at the release of porz is as follows:
drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen,
ddr1_ba[2:0], ddr1_a[15:0].
OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0],
ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0].
NOTE
ECC is not available on this device, but signal names are retained for consistency with the
DRA7xx family of devices.
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Terminal Configuration and Functions
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