DRA722_17 Datasheet, PDF (354/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
• Propagation delays and matching:
– A to C = C to D = E to F.
– Matching skew: < 60pS
– A to B < 450pS
– B to C = as small as possible (<60pS)
A
R1
0 Ω*
qspi1_sclk
D
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Locate both R2 resistors
close together near the QSPI device
B
C
R2
10 Ω
R2
10 Ω
QSPI device
clock input
qspi1_rtclk
E
F
qspi1_d[x], qspi1_cs[y]
QSPI device
IOx, CS#
SPRS906_PCB_QSPI_01
Figure 8-20. QSPI Interface High Level Schematic
NOTE
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-
tuning if needed.
8.5 Differential Interfaces
8.5.1 General Routing Guidelines
To maximize signal integrity, proper routing techniques for differential signals are important for high-speed
designs. The following general routing guidelines describe the routing guidelines for differential lanes and
differential signals.
• As much as possible, no other high-frequency signals must be routed in close proximity to the
differential pair.
• Must be routed as differential traces on the same layer. The trace width and spacing must be chosen
to yield the differential impedance value recommended.
• Minimize external components on differential lanes (like external ESD, probe points).
• Through-hole pins are not recommended.
• Differential lanes mustn’t cross image planes (ground planes).
• No sharp bend on differential lanes.
354 Applications, Implementation, and Layout
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