DRA722_17 Datasheet, PDF (238/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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GPMC_FCLK
gpmc_clk
gpmc_csi
gpmc_a27
gpmc_a[10:1]
gpmc_ben0
gpmc_ben1
gpmc_advn_ale
gpmc_oen_ren
gpmc_ad[15:0]
FA9
FA10
FA10
FA3
FA12
FA13
FA29
Address (LSB)
FA1
FA5
Address (MSB)
FA0
Valid
FA0
Valid
FA4
FA37
Data IN
Data IN
FA15
FA14
DIR
OUT
IN
OUT
gpmc_waitj
GPMC_11
Figure 7-17. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing^(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
238 Timing Requirements and Switching Characteristics
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