DRA722_17 Datasheet, PDF (148/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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Instance Name
TIMER5
TIMER6
TIMER7
Table 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
TIMER5_ICLK
TIMER5_FCLK
Clock
Type
Int
Func
Max. Clock
Allowed (MHz)
266
100
PRCM Clock Name
IPU_L3_GICLK
TIMER5_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
TIMER6_ICLK
Int
266
TIMER6_FCLK
Func
100
IPU_L3_GICLK
TIMER6_GFCLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
TIMER7_ICLK
Int
266
TIMER7_FCLK
Func
100
IPU_L3_GICLK
TIMER7_GFCLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CLKOUTMUX[0]
PLL / OSC /
Source Name
DPLL_CORE
OSC1
OSC1
RTC Oscillator
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC1
OSC1
RTC Oscillator
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC1
OSC1
RTC Oscillator
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
148 Specifications
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