DRA722_17 Datasheet, PDF (195/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-4. VIN1 IOSETs (continued)
SIGNALS
IOSET2
IOSET3
IOSET4 ⁽¹⁾
IOSET5 ⁽¹⁾
IOSET6 ⁽¹⁾
IOSET7 ⁽¹⁾
IOSET8
IOSET9
IOSET10
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin1b
vin1b_clk1
P7
6
M4
4
V1
5
N9
6
vin1b_hsync1
H5
6
H5
6
U7
5
N7
6
vin1b_vsync1
H6
6
H6
6
V6
5
R4
6
vin1b_fld1
M4
6
W2
5
P4
6
vin1b_de1
N6
6
N6
6
V7
5
P9
6
vin1b_d0
K7
6
K7
6
U4
5
R6
6
vin1b_d1
M7
6
M7
6
V2
5
T9
6
vin1b_d2
J5
6
J5
6
Y1
5
T6
6
vin1b_d3
K6
6
K6
6
W9
5
T7
6
vin1b_d4
J7
6
J7
6
V9
5
P6
6
vin1b_d5
J4
6
J4
6
U5
5
R9
6
vin1b_d6
J6
6
J6
6
V5
5
R5
6
vin1b_d7
H4
6
H4
6
V4
5
P5
6
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad
Configuration Registers.
SIGNALS
IOSET1
BALL MUX
vin2a_clk0
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
vin2a_de0
vin2a_d0
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_d5
IOSET2
BALL MUX
IOSET4
BALL MUX
E1
0
G1
0
G6
0
H7
0
G2
0
F2
0
F3
0
D1
0
E2
0
D2
0
F4
0
Table 7-5. VIN2 IOSETs
IOSET5
IOSET6
BALL MUX BALL MUX
vin2a
E1
0
V1
4
G1
0
U7
4
G6
0
V6
4
G2
1
W2
4
V7
4
F2
0
U4
4
F3
0
V2
4
D1
0
Y1
4
E2
0
W9
4
D2
0
V9
4
F4
0
U5
4
IOSET7 ⁽¹⁾
BALL MUX
B11
3
C11
3
E11
3
D11
3
B10
3
B7
3
B8
3
A7
3
A8
3
C9
3
A9
3
IOSET8 ⁽¹⁾
BALL MUX
P4
4
R3
4
T2
4
P9
4
P7
5
R6
4
T9
4
T6
4
T7
4
P6
4
R9
4
IOSET9 ⁽¹⁾
BALL MUX
P4
4
P7
4
N1
4
J7
4
H6
4
R6
4
T9
4
T6
4
T7
4
P6
4
R9
4
IOSET10 ⁽¹⁾
BALL MUX
B26
8
E21
8
F20
8
F21
8
C23
8
B14
8
J14
8
G13
8
J11
8
E12
8
F13
8
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Timing Requirements and Switching Characteristics 195