DRA722_17 Datasheet, PDF(200/408 Page) Texas Instruments – Infotainment Applications Processor

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DRA722_17 Datasheet, PDF (200/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726

SPRS956B â MARCH 2016 â REVISED JANUARY 2017

www.ti.com

BALL

C23

BALL NAME

xref_clk3

Table 7-6. Manual Functions Mapping for VIP1 2A IOSET10 (continued)

VIP_MANUAL1

A_DELAY (ps)

G_DELAY (ps)

1440

0

VIP_MANUAL2

A_DELAY (ps)

G_DELAY (ps)

1623

0

CFG REGISTER

CFG_XREF_CLK3_IN

MUXMODE

8

vin2a_de0

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring

the use of Manual IO Timings Modes. See Table 7-7 Manual Functions Mapping for VIN2A (IOSET4/5/6) for a definition of the Manual modes.

Table 7-7 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-7. Manual Functions Mapping for VIN2A (IOSET4/5/6)

BAL BALL NAME

VIP_MANUAL3

VIP_MANUAL5

CFG REGISTER

L

A_DELAY G_DELAY A_DELAY G_DELAY

0

(ps)

(ps)

(ps)

(ps)

U3 RMII_MHZ_50

_CLK

2616

1379

2798

1294

CFG_RMII_MHZ_50_CLK_I

-

N

U4

mdio_d

2558

1105

2790

954

CFG_MDIO_D_IN

-

V1 mdio_mclk

998

463

1029

431

CFG_MDIO_MCLK_IN

-

U5 rgmii0_rxc

2658

862

2896

651

CFG_RGMII0_RXC_IN

-

V5 rgmii0_rxctl

2658

1628

2844

1518

CFG_RGMII0_RXCTL_IN

-

W2 rgmii0_rxd0

2638

1123

2856

888

CFG_RGMII0_RXD0_IN

-

Y2 rgmii0_rxd1

2641

1737

2804

1702

CFG_RGMII0_RXD1_IN

-

V3 rgmii0_rxd2

2641

1676

2801

1652

CFG_RGMII0_RXD2_IN

-

V4 rgmii0_rxd3

2644

1828

2807

1790

CFG_RGMII0_RXD3_IN

-

W9 rgmii0_txc

2638

1454

2835

1396

CFG_RGMII0_TXC_IN

-

V9 rgmii0_txctl

2672

1663

2831

1640

CFG_RGMII0_TXCTL_IN

-

U6 rgmii0_txd0

2604

1442

2764

1417

CFG_RGMII0_TXD0_IN

-

V6 rgmii0_txd1

2683

1598

2843

1600

CFG_RGMII0_TXD1_IN

-

U7 rgmii0_txd2

2563

1483

2816

1344

CFG_RGMII0_TXD2_IN

-

V7 rgmii0_txd3

V2

uart3_rxd

Y1

uart3_txd

E1 vin2a_clk0

F2

vin2a_d0

F3

vin2a_d1

D3 vin2a_d10

2717

2445

2650

0

1812

1701

1720

1461

1145

1197

0

102

439

215

2913

2743

2842

0

1936

2229

2031

1310

923

1080

0

0

10

0

CFG_RGMII0_TXD3_IN

CFG_UART3_RXD_IN

CFG_UART3_TXD_IN

CFG_VIN2A_CLK0_IN

CFG_VIN2A_D0_IN

CFG_VIN2A_D1_IN

CFG_VIN2A_D10_IN

-

-

-

vin2a_clk0

vin2a_d0

vin2a_d1

vin2a_d10

MUXMODE

1

2

3

4

-

-

-

vin2a_d11

-

-

-

vin2a_d0

-

-

-

vin2a_clk0

-

-

-

vin2a_d5

-

-

-

vin2a_d6

-

-

-

vin2a_fld0

-

-

-

vin2a_d9

-

-

-

vin2a_d8

-

-

-

vin2a_d7

-

-

-

vin2a_d3

-

-

-

vin2a_d4

-

-

-

vin2a_d10

-

-

-

vin2a_vsync

0

-

-

-

vin2a_hsync

0

-

-

-

vin2a_de0

-

-

-

vin2a_d1

-

-

-

vin2a_d2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

200 Timing Requirements and Switching Characteristics

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