DRA722_17 Datasheet, PDF (348/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
8.3.7.1 Example Stack-up
Layer Assignments:
• Layer Top: Signal and Segmented Power Plane
– Processor and PMIC components placed on Top-side
• Layer 2: Gnd Plane1
• Layer 3: Signals
• Layer n: Power Plane1
• Layer n+1: Power Plane 2
• Layer n+2: Signal
• Layer n+3: Gnd Plane2
• Layer Bottom: Signal and Segmented Power Planes
– Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
• ½ oz for all signal layers.
• 1-2oz for all power plane for improved PCB heat spreading
8.3.7.2 vdd Example Analysis
Maximum acceptable PCB resistance (R_eff) between the PMIC and Processor input power balls should not
exceed 10mΩ.
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.0nH (ESL NOT included)
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 57mΩ at 20MHz.
Table 8-7. Example PCB vdd PI Analysis Summary
Parameter
OPP
Clocking Rate
Voltage Level
Max Current Draw
Max Effective Resistance: Power
Inductor Segment Total R_eff
Max Loop Inductance
Impedance Target
Recommendation
OPP_NOM
266 MHz
1V
1A
10mΩ
2.0nH
57mΩ F<20Mhz
Example PCB
1V
1A
9.7 mΩ
0.97 –1.75nH
57mΩ F<20Mhz
348 Applications, Implementation, and Layout
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