DRA722_17 Datasheet, PDF (126/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
5 Specifications
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
NOTE
The index numbers 1 and 2 which is part of the EMIF1 signal prefixes (ddr1_*) listed in
Table 4-8, EMIF Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1
type of SDRAM memories.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
5.1 Absolute Maximum Ratings
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those listed under Section 5.4, Recommended Operating Conditions, is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Table 5-1. Absolute Maximum Rating Over Junction Temperature Range
V_SUPPLY (Steady-State)
PARAMETER⁽¹⁾
Supply Voltage Ranges (Steady-
State)
MIN
Core (vdd, vdd_mpu, vdd_gpu,
-0.3
vdd_dsp, vdd_iva, vdd_rtc)
Analog (vdda_usb1, vdda_usb2,
-0.3
vdda_per, vdda_ddr, vdda_debug,
vdda_mpu_abe, vdda_usb3,
vdda_csi, vdda_core_gmac,
vdda_pll_spare, vdda_dsp_iva,
vdda_gpu, dda_hdmi, vdda_pcie,
vdda_pcie0, vdda_sata,
vdda_video, vdda_osc, vdda_rtc)
Analog 3.3V (vdda33v_usb1,
-0.3
vdda33v_usb2)
vdds18v, vdds18v_ddr1,
-0.3
vdds_mlbp, vdds_ddr1
vddshv1-11 (1.8V mode)
-0.3
vddshv1-7 (3.3V mode), vddshv9-11 -0.3
(3.3V mode)
vddshv8 (3.3V mode)
-0.3
MAX
1.5
2.0
3.8
2.1
2.1
3.8
3.6
UNIT
V
V
V
V
V
V
V
126 Specifications
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