DRA722_17 Datasheet, PDF (287/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-68 and Figure 7-53 present timing requirements for MIIn in receive operation.
7.23.1 GMAC MII Timings
Table 7-68. Timing Requirements for miin_rxclk - MII Operation
NO.
PARAMETER
DESCRIPTION
1
t_{c(RX_CLK)}
Cycle time, miin_rxclk
2
t_{w(RX_CLKH)}
Pulse duration, miin_rxclk high
3
t_{w(RX_CLKL)}
Pulse duration, miin_rxclk low
4
t_{t(RX_CLK)}
Transition time, miin_rxclk
SPEED
MIN
10 Mbps
400
100 Mbps
40
10 Mbps
140
100 Mbps
14
10 Mbps
140
100 Mbps
14
10 Mbps
100 Mbps
MAX
260
26
260
26
3
3
miin_rxclk
1
2
4
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
4
SPRS906_TIMING_GMAC_MIIRXCLK_01
Figure 7-53. Clock Timing (GMAC Receive) - MIIn operation
Table 7-69 and Figure 7-54 present timing requirements for MIIn in transmit operation.
Table 7-69. Timing Requirements for miin_txclk - MII Operation
NO.
PARAMETER
DESCRIPTION
1
t_{c(TX_CLK)}
Cycle time, miin_txclk
2
t_{w(TX_CLKH)}
Pulse duration, miin_txclk high
3
t_{w(TX_CLKL)}
Pulse duration, miin_txclk low
4
t_{t(TX_CLK)}
Transition time, miin_txclk
SPEED
MIN
10 Mbps
400
100 Mbps
40
10 Mbps
140
100 Mbps
14
10 Mbps
140
100 Mbps
14
10 Mbps
100 Mbps
MAX
260
26
260
26
3
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 287
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