DRA722_17 Datasheet, PDF (120/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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Table 4-30. PRCM Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
clkout2
Device Clock output 2. Can be used externally for devices with non-
O
critical timing requirements, or for debug.
D18 / N1
clkout3
Device Clock output 3. Can be used xternally for devices with non-
O
C23
critical timing requirements, or for debug.
rstoutn
Reset out (Active low). This pin asserts low in response to any global
O
F23
reset condition on the device. ⁽²⁾
resetn
Device Reset Input
I
E23
porz
Power on Reset (active low). This pin must be asserted low until all
I
F22
device supplies are valid (see reset sequence/requirements)
xref_clk0
External Reference Clock 0. For Audio and other Peripherals.
I
D18
xref_clk1
External Reference Clock 1. For Audio and other Peripherals.
I
E17
xref_clk2
External Reference Clock 2. For Audio and other Peripherals.
I
B26
xref_clk3
External Reference Clock 3. For Audio and other Peripherals.
I
C23
xi_osc0
System Oscillator OSC0 Crystal input / LVCMOS clock input.
I
Functions as the input connection to a crystal when the internal
oscillator OSC0 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used.
AE15
xo_osc0
System Oscillator OSC0 Crystal output
O
AD15
xi_osc1
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.
I
Functions as the input connection to a crystal when the internal
oscillator OSC1 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used
AC15
xo_osc1
Auxiliary Oscillator OSC1 Crystal output
O
RMII_MHZ_50_CLK⁽¹⁾
RMII Reference Clock (50MHz). This pin is an input when external
IO
reference is used or output when internal reference is used.
AC13
U3
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it
must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.
4.4.26.3 Real-Time Clock (RTC) Interface
NOTE
For more information, see the Real-Time Clock (RTC) chapter of the device TRM.
Table 4-31. RTC Signal Descriptions
SIGNAL NAME
Wakeup0
Wakeup3
rtc_porz
rtc_osc_xi_clkin32
rtc_osc_xo
rtc_iso⁽¹⁾
on_off
DESCRIPTION
RTC External Wakeup Input 0
RTC External Wakeup Input 3
RTC Power Domain Power-On Reset Input
RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as
an RTC clock input when an external oscillator is used.
RTC Oscillator Output
RTC domain Isolation Signal
RTC Power Enable output pin
TYPE
I
I
I
I
O
I
O
BALL
AD17
AC16
AB17
AE14
AD14
AF14
Y11
120 Terminal Configuration and Functions
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