DRA722_17 Datasheet, PDF (184/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
For more information, see:
NOTE
• Power, Reset, and Clock Management / Clock Management Functional / Internal Clock
Sources / Generators / Generic DPLL Overview Section
and
• Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module. They are of two types: type A and type B DPLLs.
• They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
• They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
• DPLL_MPU: It supplies the MPU subsystem clocking internally.
• DPLL_IVA: It feeds the IVA subsystem clocking.
• DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
• DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a
96-MHz functional clock to subsystems and peripherals.
• DPLL_ABE: It provides clocks to various modules within the device.
• DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
• DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
• DPLL_DSP: It feeds the DSP Subsystem clocking.
• DPLL_GPU: It supplies clock for the GPU Subsystem.
• DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
• DPLL_PCIE_REF: It provides reference clock for the APLL_PCIE in PCIE Subsystem.
• APLL_PCIE: It feeds clocks for the device Peripheral Component Interconnect Express (PCIe)
controllers.
NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
• DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_DSP, DPLL_GPU, APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
• DPLL_VIDEO1; (It is controlled from DSS)
• DPLL_HDMI; (It is controlled from DSS)
• DPLL_SATA; (It is controlled from SATA)
• DPLL_DEBUG; (It is controlled from DEBUGSS)
• DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
NOTE
For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
184 Clock Specifications
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