DRA722_17 Datasheet, PDF (327/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
TCK
TDO
3
TDI/TMS
1
1a
1b
2
4
Figure 7-95. JTAG Timing
SPRS906_TIMING_JTAG_01
Table 7-142, Table 7-143 and Figure 7-96 assume testing over the recommended operating conditions
and electrical characteristic conditions below.
Table 7-142. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
1
1a
1b
3
4
PARAMETER
t_c(TCK)
t_w(TCKH)
t_w(TCKL)
t_su(TDI-TCK)
t_su(TMS-TCK)
t_h(TCK-TDI)
t_h(TCK-TMS)
DESCRIPTION
Cycle time, TCK
Pulse duration, TCK high (40% of t_c)
Pulse duration, TCK low (40% of t_c)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
MIN
62.29
24.92
24.92
6.23
6.23
31.15
31.15
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Table 7-143. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
5
t_d(TCK-RTCK)
6
t_c(RTCK)
7
t_w(RTCKH)
8
t_w(RTCKL)
DESCRIPTION
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the ARM is in the scan chain, the delay
time is a function of the ARM functional clock).
Cycle time, RTCK
Pulse duration, RTCK high (40% of t_c)
Pulse duration, RTCK low (40% of t_c)
MIN
0
62.29
24.92
24.92
MAX
27
UNIT
ns
ns
ns
ns
TCK
5
6
7
8
RTCK
Figure 7-96. JTAG With RTCK Timing
SPRS906_TIMING_JTAG_02
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Timing Requirements and Switching Characteristics 327
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