DRA722_17 Datasheet, PDF (392/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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Rtt
A2
A3
AT
Vtt
=
SPRS906_PCB_DDR3_17
Figure 8-56. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
8.7.2.15.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
8.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 8-57 shows the topology of the CK net classes and Figure 8-58 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR Differential CK Input Buffer
+–
Processor
+
Differential Clock
Output Buffer
–
Clock Parallel
Terminator
Rcp
DDR_1V5
A1
A2
AT
Cac
Rcp
0.1 µF
A1
A2
AT
Routed as Differential Pair
Figure 8-57. CK Topology for One DDR3 Device
SPRS906_PCB_DDR3_18
392 Applications, Implementation, and Layout
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