DRA722_17 Datasheet, PDF (247/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-31, Table 7-32 and Figure 7-23 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
Table 7-31. Timing Requirements for I2C Input Timings⁽¹⁾
NO. PARAMETER
DESCRIPTION
1
t_c(SCL)
2
t_{su(SCLH-SDAL)}
3
t_h(SDAL-SCLL)
4
t_w(SCLL)
5
t_w(SCLH)
6
t_{su(SDAV-SCLH)}
7
t_h(SCLL-SDAV)
8
t_w(SDAH)
9
t_r(SDA)
Cycle time, SCL
Setup time, SCL high before SDA low (for a
repeated START condition)
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
Pulse duration, SDA high between STOP and
START conditions
Rise time, SDA
STANDARD MODE
MIN
MAX
10
4.7
4
4.7
4
250
0⁽³⁾
3.45⁽⁴⁾
4.7
1000
FAST MODE
MIN
MAX
2.5
0.6
0.6
1.3
0.6
100⁽²⁾
0⁽³⁾
1.3
20 + 0.1C_b
(5)
0.9⁽⁴⁾
300⁽³⁾
UNIT
µs
µs
µs
µs
µs
ns
µs
µs
ns
10 t_r(SCL)
Rise time, SCL
1000
20 + 0.1C_b
(5)
300⁽³⁾
ns
11 t_f(SDA)
Fall time, SDA
300
20 + 0.1C_b
(5)
300⁽³⁾
ns
12 t_f(SCL)
Fall time, SCL
300
20 + 0.1C_b
(5)
300⁽³⁾
ns
13 t_{su(SCLH-SDAH)}
Setup time, SCL high before SDA high (for
STOP condition)
4
0.6
µs
14 t_w(SP)
15 C_b ⁽⁵⁾
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50
ns
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
(5) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Table 7-32. Timing Requirements for I²C HS-Mode (I²C3/4/5/6 Only)⁽¹⁾
NO. PARAMETER
DESCRIPTION
C_b = 100 pF MAX
MIN
MAX
C_b = 400 pF ⁽²⁾
MIN
MAX
1
t_c(SCL)
2
t_{su(SCLH-SDAL)}
Cycle time, SCL
Set-up time, SCL high before
SDA low (for a repeated START
condition)
0.294
160
0.588
160
3
t_h(SDAL-SCLL)
Hold time, SCL low after SDA
160
160
low (for a repeated START
condition)
4
t_w(SCLL)
LOW period of the SCLH clock
160
320
5
t_w(SCLH)
HIGH period of the SCLH clock
60
120
6
t_{su(SDAV-SCLH)}
Setup time, SDA valid vefore
10
10
SCL high
UNIT
µs
ns
ns
ns
ns
ns
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 247
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726