DRA722_17 Datasheet, PDF (278/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
McASP
CLKX
FSX
TXDATA
SoC IOs
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CLKR
FSR
RXDATA
SPRS906_MCASP_uc_08
Figure 7-50. McASP1-8 CO-FI- - SYNC Mode
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
278 Timing Requirements and Switching Characteristics
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