DRA722_17 Datasheet, PDF (262/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
PHA=1
cs
Q5
Q4
POL=1
sclk
Q1
Q3 Q2
Q7
d[0]
Q6
Q6
Command Command
Bit n-1
Bit n-2
Q6
Q6
Q8
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
PHA=0
cs
POL=0
sclk
Q7
d[0]
Figure 7-39. QSPI Write (Clock Mode 3)
SPRS85v_TIMING_OSPI1_03
Q4
Q1
Q2 Q3
Q9 Q6
Command Command
Bit n-1
Bit n-2
Q5
Q6
Q6
Q8
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
Figure 7-40. QSPI Write (Clock Mode 0)
SPRS85v_TIMING_OSPI1_04
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
262 Timing Requirements and Switching Characteristics
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