DRA722_17 Datasheet, PDF (207/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-10. Manual Functions Mapping for VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) (continued)
BALL
BALL NAME
VIP_MANUAL8
VIP_MANUAL13
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
3
4
5
F10
vout1_d2
2170
237
2624
0
CFG_VOUT1_D2_IN
vin2a_d18
-
-
C9
vout1_d20
1942
512
2579
91
CFG_VOUT1_D20_IN
vin2a_d4
-
-
A9
vout1_d21
1997
141
2324
0
CFG_VOUT1_D21_IN
vin2a_d5
-
-
B9
vout1_d22
1949
0
2165
0
CFG_VOUT1_D22_IN
vin2a_d6
-
-
A10
vout1_d23
1871
704
2522
269
CFG_VOUT1_D23_IN
vin2a_d7
-
-
G11
vout1_d3
2319
417
2740
191
CFG_VOUT1_D3_IN
vin2a_d19
-
-
E9
vout1_d4
2300
369
2739
137
CFG_VOUT1_D4_IN
vin2a_d20
-
-
F9
vout1_d5
1923
579
2527
191
CFG_VOUT1_D5_IN
vin2a_d21
-
-
F8
vout1_d6
2148
396
2622
138
CFG_VOUT1_D6_IN
vin2a_d22
-
-
E7
vout1_d7
2212
335
2653
110
CFG_VOUT1_D7_IN
vin2a_d23
-
-
E8
vout1_d8
1962
573
2573
178
CFG_VOUT1_D8_IN
vin2a_d8
-
-
D9
vout1_d9
2312
335
2725
138
CFG_VOUT1_D9_IN
vin2a_d9
-
-
B10
vout1_de
1973
414
2551
52
CFG_VOUT1_DE_IN
vin2a_de0
-
-
B11
vout1_fld
0
0
0
0
CFG_VOUT1_FLD_IN
vin2a_clk0
-
-
C11
vout1_hsync
1813
261
2277
0
CFG_VOUT1_HSYNC_IN
vin2a_hsync0
-
-
E11
vout1_vsync
1665
0
1881
0
CFG_VOUT1_VSYNC_IN
vin2a_vsync0
-
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-11 Manual Functions Mapping for VIN1B (IOSET6) for a definition of the Manual modes.
Table 7-11 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL
R6
T9
N9
P9
P4
T6
T7
P6
BALL NAME
gpmc_a0
gpmc_a1
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a2
gpmc_a3
gpmc_a4
Table 7-11. Manual Functions Mapping for VIN1B (IOSET6)
VIP_MANUAL9
A_DELAY (ps) G_DELAY (ps)
1873
702
1629
772
0
0
1851
1011
2009
601
1734
898
1757
1076
1794
893
VIP_MANUAL14
A_DELAY (ps) G_DELAY (ps)
2202
441
2057
413
0
0
2126
856
2289
327
2131
573
2106
812
2164
559
CFG REGISTER
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A10_IN
CFG_GPMC_A11_IN
CFG_GPMC_A12_IN
CFG_GPMC_A2_IN
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
MUXMODE
5
6
-
vin1b_d0
-
vin1b_d1
-
vin1b_clk1
-
vin1b_de1
-
vin1b_fld1
-
vin1b_d2
-
vin1b_d3
-
vin1b_d4
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Timing Requirements and Switching Characteristics 207