DRA722_17 Datasheet, PDF (377/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
• Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
8.7.2 DDR3 Board Design and Layout Guidelines
8.7.2.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-29 and
Figure 8-40.
Table 8-29. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
PARAMETER
MIN
MAX
UNIT
1 t_{c(DDR_CLK)}
Cycle time, DDR_CLK
1.5
2.5⁽¹⁾
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS906_PCB_DDR3_01
Figure 8-40. DDR3 Memory Controller Clock Timing
8.7.2.2 DDR3 EMIF
The processor contains one DDR3 EMIF.
8.7.2.3 DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting,
Table 8-30 summarizes the supported device configurations.
NUMBER OF DDR3 DEVICES
1
2
2
2
3
4
4
5
Table 8-30. Supported DDR3 Device Combinations
DDR3 DEVICE WIDTH (BITS)
16
8
16
16
16
8
8
8
MIRRORED?
N
Y⁽¹⁾
N
Y⁽¹⁾
N⁽³⁾
N
Y⁽²⁾
N ⁽³⁾
DDR3 EMIF WIDTH (BITS)
16
16
32
32
32
32
32
32
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Applications, Implementation, and Layout 377
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