DRA722_17 Datasheet, PDF (316/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 7-119. Manual Functions Mapping for MMC2 (continued)
BAL BALL NAME MMC2_MANUAL1
L
A_DELAY G_DELAY
(ps)
(ps)
M7 gpmc_a20
0
0
J5 gpmc_a21
0
0
K6 gpmc_a22
0
0
J4 gpmc_a24
0
0
J6 gpmc_a25
0
0
H4 gpmc_a26
0
0
H5 gpmc_a27
0
0
H6 gpmc_cs1
0
0
MMC2_MANUAL2
A_DELAY G_DELAY
(ps)
(ps)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MMC2_MANUAL3
A_DELAY G_DELAY
(ps)
(ps)
231
0
39
0
91
0
176
0
0
0
101
0
0
0
360
0
CFG REGISTER
MUXMODE
1
CFG_GPMC_A20_OEN mmc2_dat5
CFG_GPMC_A21_OEN mmc2_dat6
CFG_GPMC_A22_OEN mmc2_dat7
CFG_GPMC_A24_OEN mmc2_dat0
CFG_GPMC_A25_OEN mmc2_dat1
CFG_GPMC_A26_OEN mmc2_dat2
CFG_GPMC_A27_OEN mmc2_dat3
CFG_GPMC_CS1_OE mmc2_cmd
N
7.25.3 MMC3 and MMC4-SDIO/SD
MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic
SDIO devices, it supports the following applications:
• MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR
• MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR
• MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half
cycle
• MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
• MMC3 8-bit data, UHS-I SDR50
NOTE
The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj.
NOTE
For more information, see the MMC/SDIO chapter of the Device TRM.
7.25.3.1 MMC3 and MMC4, SD Default Speed
Figure 7-84 , Figure 7-85, and Table 7-120 through Table 7-123 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.
Table 7-120. Timing Requirements for MMC3 - Default Speed Mode ⁽¹⁾
NO. PARAMETER
DS5
t_{su(cmdV-clkH)}
DS6
t_h(clkH-cmdV)
DS7 t_su(dV-clkH)
DS8 t_h(clkH-dV)
(1) i in [i:0] = 7
DESCRIPTION
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
5.11
20.46
5.11
20.46
MAX
UNIT
ns
ns
ns
ns
Table 7-121. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode ⁽²⁾
NO.
DS0
DS1
PARAMETER
fop(clk)
t_w(clkH)
DESCRIPTION
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
MIN
0.5*P-
0.270 ⁽¹⁾
MAX
24
UNIT
MHz
ns
316 Timing Requirements and Switching Characteristics
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