DRA722_17 Datasheet, PDF (171/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails.
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: resetn/porz must remain low a minimum of 12P⁽¹⁵⁾ after xi_osc0 is stable and at a valid frequency.
(12) Setup time: sysboot[15:0] pins must be valid 2P⁽¹⁵⁾ before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P⁽¹⁵⁾ after porz is de-asserted high.
(14) resetn to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
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Specifications 171