DRA722_17 Datasheet, PDF (208/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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BALL
R9
R5
P5
N7
R4
U4
V1
U5
V5
W2
V4
W9
V9
V6
U7
V7
V2
Y1
BALL NAME
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
mdio_d
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
uart3_txd
Table 7-11. Manual Functions Mapping for VIN1B (IOSET6) (continued)
VIP_MANUAL9
A_DELAY (ps) G_DELAY (ps)
1726
853
1792
612
2117
610
1758
653
1705
899
1945
671
255
119
2057
909
2121
1139
2070
655
2092
1357
2088
1205
2143
1383
2078
1189
1928
1125
2255
971
1829
747
2030
837
VIP_MANUAL14
A_DELAY (ps) G_DELAY (ps)
2120
523
2153
338
2389
304
2140
308
2067
646
2265
414
337
0
2341
646
2323
988
2336
340
2306
1216
2328
1079
2312
1311
2324
1065
2306
763
2401
846
2220
400
2324
568
CFG REGISTER
CFG_GPMC_A5_IN
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
CFG_GPMC_A8_IN
CFG_GPMC_A9_IN
CFG_MDIO_D_IN
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
MUXMODE
5
6
-
vin1b_d5
-
vin1b_d6
-
vin1b_d7
-
vin1b_hsync1
-
vin1b_vsync1
vin1b_d0
-
vin1b_clk1
-
vin1b_d5
-
vin1b_d6
-
vin1b_fld1
-
vin1b_d7
-
vin1b_d3
-
vin1b_d4
-
vin1b_vsync1
-
vin1b_hsync1
-
vin1b_de1
-
vin1b_d1
-
vin1b_d2
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-12 Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET9) for a definition of the
Manual modes.
Table 7-12 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL
K7
M7
J5
K6
J7
J4
BALL NAME
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
Table 7-12. Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET9)
VIP_MANUAL10
A_DELAY (ps) G_DELAY (ps)
1600
943
1440
621
1602
1066
1395
983
1571
716
1463
832
VIP_MANUAL11
A_DELAY (ps) G_DELAY (ps)
2023
477
1875
136
2021
604
1822
519
2045
200
1893
396
CFG REGISTER
CFG_GPMC_A19_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A24_IN
MUXMODE
4
6
vin2a_d12
vin2b_d0
vin2a_d13
vin2b_d1
vin2a_d14
vin2b_d2
vin2a_d15
vin2b_d3
vin2a_fld0
vin2b_d4
-
vin2b_d5
208 Timing Requirements and Switching Characteristics
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