DRA722_17 Datasheet, PDF (346/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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• Support for power sequencing requirements (refer to Section 5.9 Power Supply Sequences)
• Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,
thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
• The AVS voltage of active rail in the combined rail needs to be used to set the power supply
• The decoupling capacitance should be set according to the active rail in the combined rail
Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS659039 PMIC.
Table 8-4. TPS659039 Power Supply Connections⁽¹⁾
SMPS
SMPS1/2/3⁽²⁾
SMPS3⁽²⁾
Valid Combination 1:
Reference Platform
vdd_mpu
vdds_ddr1
Valid Combination 2:
MPU Centric
vdd_mpu
vdds_ddr1
TPS659039 Current
Rating Limitation ^{(3) (4)}
SMPS1/2: 6A
SMPS1/2/3: 9A
SMPS3: 3A
SMPS4/5
vdd_dsp
vdd_dsp, vdd_gpu,
vdd_iva
SMPS4/5: 4A
SMPS6
vdd_gpu
vdd
SMPS6: 2-3A
(BOOST_CURRENT=0/1)
SMPS7
vdd
Free
2A
SMPS8
vdd_iva
Free
1A
SMPS9
vdds18v
vdds18v
1A
(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(2) Dual phase (SMPS1/2) can be used as long as the peak power consumption is maintained below the SMPS1/2 capacity
(a) For the latest rated output current specifications for the TPS659039 device, please refer to the PMIC data manual.
(b) MPU power consumption is highly system dependent. A detailed power consumption estimate must be performed to confirm
compatibility. Example: Single vs Dual MPU, OPP_NOM vs OPP_OD vs OPP_HIGH, TPS659039 configured with V_I≥3V vs V_I<3V,
etc. Contact your TI representative for details.
(3) Refer to the PMIC data manual for the latest TPS659039 specifications.
(4) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.
Table 8-5 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS65917 PMIC.
Table 8-5. TPS65917 Power Supply Connections
TPS65917
SMPS1
Valid
Combination
1:
vdd_mpu
Valid
Combination 2:
vdd_mpu
TPS65917
Current Rating
Limitation ^{(1) (3)}
3.5A
346 Applications, Implementation, and Layout
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