DRA722_17 Datasheet, PDF (373/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
8.5.6.2.2.3 Pair Length Matching
Each signal in the differential pair should be matched to within 5 mils of its matching differential signal.
Length matching should be done as close to the mismatch as possible.
8.5.6.3 LJCB_REFN/P Connections
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two
modes of Common Refclk Rx Architecture are supported:
• External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device
and the link partner
• Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link
partner
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to
the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.
Alternatively, an LVDS clock source can be used with the following additional requirements:
• External AC coupling capacitors described in Table 8-25 should be populated at the ljcb_clkn /
ljcb_clkp inputs.
• All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer
should be followed.
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on
the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-
side termination to ground described in Table 8-26 is required on both of the ljcb_clkn / ljcb_clkp outputs
in this mode.
Table 8-25. LJCB_REFN/P Requirements in External LVDS REFCLK Mode
PARAMETER
MIN
TYP
MAX
UNIT
ljcb_clkn / ljcb_clkp AC coupling capacitor value
ljcb_clkn / ljcb_clkp AC coupling capacitor package size
100
0402
0603
nF
EIA⁽¹⁾⁽²⁾
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
Table 8-26. LJCB_REFN/P Requirements in Output REFCLK Mode
PARAMETER
MIN
TYP
MAX
ljcb_clkn / ljcb_clkp near-side termination to ground value
47.5
50
52.5
UNIT
Ohms
8.5.7 CSI2 Board Design and Routing Guidelines
The MIPI D-PHY signals include the CSI2_0 and CSI2_1 camera serial interfaces to or from the Device.
For more information regarding the MIPI-PHY signals and corresponding balls, see Table 4-7, CSI2 Signal
Descriptions.
For more information, you can also see the MIPI D-PHY specification v1-01-00_r0-03 (specifically the
Interconnect and Lane Configuration and Annex B Interconnect Design Guidelines chapters).
In the next section, the PCB guidelines of the following differential interfaces are presented:
• CSI2_0 and CSI2_1 MIPI CSI-2 at 1.5 Gbps
Table 8-27 lists the MIPI D-PHY interface signals in the Device.
SIGNAL NAME
csi2_0_dx0
Table 8-27. MIPI D-PHY Interface Signals in the Device
BOTTOM BALL
AE1
SIGNAL NAME
csi2_0_dy0
BOTTOM BALL
AD2
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Applications, Implementation, and Layout 373
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