DRA722_17 Datasheet, PDF (395/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
8.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 8-63 and Figure 8-64 show the DQS and DQ/DM routing.
DQSn+
DQSn-
Routed Differentially
DQS
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_24
Figure 8-63. DQS Routing With Any Number of Allowed DDR3 Devices
Dn
DQ and DM
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_25
Figure 8-64. DQ/DM Routing With Any Number of Allowed DDR3 Devices
8.7.2.17 Routing Specification
8.7.2.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
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Applications, Implementation, and Layout 395
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