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| DRA722_17 Datasheet, PDF (293/408 Pages) Texas Instruments – Infotainment Applications Processor | |||
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www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B â MARCH 2016 â REVISED JANUARY 2017
BALL
U3
U6
V6
U7
V7
Table 7-81. Manual Functions Mapping for GMAC RMII0
BALL NAME
RMII_MHZ_50_CLK
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
GMAC_RMII0_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
0
0
2444
804
2453
981
2356
847
2415
993
CFG REGISTER
MUXMODE
0
1
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
RMII_MHZ_50_CLK
rmii0_rxd0
rmii0_rxd1
rmii0_rxer
rmii0_crs
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-82 Manual
Functions Mapping for GMAC RMII1 for a definition of the Manual modes.
Table 7-82 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
BALL
U3
V9
W9
Y1
V2
Table 7-82. Manual Functions Mapping for GMAC RMII1
BALL NAME
RMII_MHZ_50_CLK
rgmii0_txctl
rgmii0_txc
uart3_txd
uart3_rxd
GMAC_RMII1_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
0
0
2450
909
2327
926
2553
443
1943
1110
CFG REGISTER
MUXMODE
0
2
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXC_IN
CFG_UART3_TXD_IN
CFG_UART3_RXD_IN
RMII_MHZ_50_CLK
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_crs
7.23.4 GMAC RGMII Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-83, Table 7-84 and Figure 7-60 present timing requirements for receive RGMIIn operation.
Table 7-83. Timing Requirements for rgmiin_rxc - RGMIIn Operation
NO. PARAMETER
1
tc(TXC)
DESCRIPTION
Cycle time, rgmiin_txc
2
tw(TXCH)
Pulse duration, rgmiin_txc high
3
tw(TXCL)
Pulse duration, rgmiin_txc low
4
tt(TXC)
Transition time, rgmiin_txc
SPEED
MIN
10 Mbps
360
100 Mbps
36
1000 Mbps
7.2
10 Mbps
160
100 Mbps
16
1000 Mbps
3.6
10 Mbps
160
100 Mbps
16
1000 Mbps
3.6
10 Mbps
100 Mbps
1000 Mbps
MAX
440
44
8.8
240
24
4.4
240
24
4.4
0.75
0.75
0.75
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2016â2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 293
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Product Folder Links: DRA722 DRA724 DRA725 DRA726
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