DRA722_17 Datasheet, PDF (295/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-86. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps ⁽¹⁾
NO. PARAMETER DESCRIPTION
MODE
MIN MAX UNIT
5
t_osu(TXD-TXC)
Output Setup time, transmit selected signals valid to
RGMII0, Internal Delay
1.05
ns
rgmiin_txc high/low
Enabled, 1000 Mbps
(2)
RGMII0, Internal Delay
1.2
ns
Enabled, 10/100 Mbps
RGMII1, Internal Delay
1.05
ns
Enabled, 1000 Mbps
(3)
RGMII1, Internal Delay
1.2
ns
Enabled, 10/100 Mbps
6
t_oh(TXC-TXD)
Output Hold time, transmit selected signals valid after
RGMII0, Internal Delay
1.05
ns
rgmiin_txc high/low
Enabled, 1000 Mbps
(2)
RGMII0, Internal Delay
1.2
ns
Enabled, 10/100 Mbps
RGMII1, Internal Delay
1.05
ns
Enabled, 1000 Mbps
(3)
RGMII1, Internal Delay
1.2
ns
Enabled, 10/100 Mbps
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of
rgmii0_txc.
(3) RGMII1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of
rgmii1_txc.
rgmiin_txc^(A)
[internal delay enabled]
1
4
2
3
4
rgmiin_txd[3:0]^(B)
rgmiin_txctl^(B)
1st Half-byte 2nd Half-byte
TXEN
TXERR
5
6
SPRS906_TIMING_GMAC_RGMIITX_09
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 7-61. GMAC Transmit Interface Timing RGMIIn operation
In Table 7-87 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
SIGNALS
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxd3
rgmii1_rxd2
Table 7-87. GMAC RGMII IOSETs
BALL
C3
C4
B2
D6
B3
B4
IOSET3
MUX
3
3
3
3
3
3
BALL
IOSET4
MUX
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Timing Requirements and Switching Characteristics 295
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