DRA722_17 Datasheet, PDF (310/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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7.25.2.1 Standard JC64 SDR, 8-bit data, half cycle
Table 7-111 and Table 7-112 present Timing requirements and Switching characteristics for MMC2 - Standart SDR in receiver and transmitter
mode (see Figure 7-77 and Figure 7-78).
NO.
SSDR5
SSDR6
SSDR7
SSDR8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
Table 7-111. Timing Requirements for MMC2 - JC64 Standard SDR Mode
DESCRIPTION
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
MIN
13.19
8.4
13.19
8.4
MAX
UNIT
ns
ns
ns
ns
310 Timing Requirements and Switching Characteristics
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