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DRA722_17 Datasheet, PDF (96/408 Pages) Texas Instruments – Infotainment Applications Processor
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 4-8. EMIF Signal Descriptions (continued)
SIGNAL NAME
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqm_ecc
ddr1_dqs0
ddr1_dqsn0
ddr1_dqs1
ddr1_dqsn1
ddr1_dqs2
ddr1_dqsn2
ddr1_dqs3
ddr1_dqsn3
ddr1_dqs_ecc
ddr1_dqsn_ecc
ddr1_vref0
DESCRIPTION
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 ECC Data Mask
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 0 invert
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 1 invert
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 2 invert
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 3 invert
EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when
writing and input when reading.
EMIF1 ECC Complementary Data strobe
Reference Power Supply EMIF1
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A
4.4.6 General-Purpose Memory Controller (GPMC)
BALL
AA23
Y22
Y23
AA24
Y24
AA26
AA25
AA28
W22
V23
W19
W23
Y25
V24
V25
Y26
AD23
AB23
AC26
AA27
V26
AH25
AG25
AE27
AE28
AD27
AD28
Y28
Y27
V27
V28
Y18
NOTE
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the device TRM.
SIGNAL NAME
gpmc_ad0
Table 4-9. GPMC Signal Descriptions
DESCRIPTION
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
TYPE
IO
BALL
M6
96
Terminal Configuration and Functions
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