DRA722_17 Datasheet, PDF (381/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
8.7.2.5 Compatible JEDEC DDR3 Devices
Table 8-31 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1333 devices in the x8 or x16 widths.
Table 8-31. Compatible JEDEC DDR3 Devices (Per Interface)
N
PARAMETER
O.
1 JEDEC DDR3 device speed grade⁽¹⁾
CONDITION
DDR clock rate = 400MHz
MIN
DDR3-800
MAX
DDR3-1600
UNIT
400MHz< DDR clock rate ≤ 533MHz
DDR3-1066
DDR3-1600
533MHz< DDR clock rate ≤ 667MHz
DDR3-1333
DDR3-1600
2 JEDEC DDR3 device bit width
3 JEDEC DDR3 device count⁽²⁾
x8
x16
Bits
2
4
Devices
(1) Refer to Table 8-29 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see Section 8.7.2.4, Figure 8-41, and Figure 8-42.
8.7.2.6 PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-32.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in
Table 8-33.
LAYER
1
2
3
4
5
6
Table 8-32. Six-Layer PCB Stackup Suggestion
TYPE
Signal
Plane
Plane
Plane
Plane
Signal
DESCRIPTION
Top routing mostly vertical
Ground
Split power plane
Split power plane or Internal routing
Ground
Bottom routing mostly horizontal
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Applications, Implementation, and Layout 381
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