DRA722_17 Datasheet, PDF (261/408 Pages) Texas Instruments – Infotainment Applications Processor

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PHA=0
cs
POL=0
sclk
Q4
Q1
Q2 Q3
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Q5
POL=0
rtclk
Q7
d[0]
Q9 ^Q6
Command Command
Bit n-1
Bit n-2
d[3:1]
Q12 Q13
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
Q12 Q13
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
Figure 7-38. QSPI Read (Clock Mode 0)
SPRS85v_TIMING_OSPI1_02
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-44. Timing Requirements for QSPI⁽³⁾⁽²⁾
NO. PARAMETER DESCRIPTION
Q2
t_su(D-RTCLK)
Setup time, d[3:0] valid before falling rtclk edge
t_su(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
Q13 t_h(RTCLK-D)
Hold time, d[3:0] valid after falling rtclk edge
t_h(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
Q14 t_su(D-SCLK)
Q15 t_h(SCLK-D)
Setup time, final d[3:0] bit valid before final falling sclk
edge
Hold time, final d[3:0] bit valid after final falling sclk
edge
MODE
Default Timing Mode,
Clock Mode 0
Default Timing Mode,
Clock Mode 3
Default Timing Mode,
Clock Mode 0
Default Timing Mode,
Clock Mode 3
Default Timing Mode,
Clock Mode 3
Default Timing Mode,
Clock Mode 3
MIN MAX
4.6
12.3
-0.1
0.1
12.3-P
(1)
0.1+P
(1)
UNIT
ns
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 261
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