DRA722_17 Datasheet, PDF (288/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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1
2
4
3
miin_txclk
4
SPRS906_TIMING_GMAC_MIITXCLK_02
Figure 7-54. Clock Timing (GMAC Transmit) - MIIn operation
Table 7-70 and Figure 7-55 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.
Table 7-70. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
NO.
1
2
PARAMETER
t_{su(RXD-RX_CLK)}
t_{su(RX_DV-RX_CLK)}
t_{su(RX_ER-RX_CLK)}
t_{h(RX_CLK-RXD)}
t_{h(RX_CLK-RX_DV)}
t_{h(RX_CLK-RX_ER)}
DESCRIPTION
Setup time, receive selected signals valid before miin_rxclk
Hold time, receive selected signals valid after miin_rxclk
MIN
MAX
8
8
UNIT
ns
ns
1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
Figure 7-55. GMAC Receive Interface Timing MIIn operation
SPRS906_TIMING_GMAC_MIIRCV_03
Table 7-71 and Figure 7-56 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
Table 7-71. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
1
t_{d(TX_CLK-TXD)}
t_{d(TX_CLK-TX_EN)}
DESCRIPTION
Delay time, miin_txclk to transmit selected signals valid
MIN
MAX
UNIT
0
25
ns
1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen (outputs)
Figure 7-56. GMAC Transmit Interface Timing MIIn operation
SPRS906_TIMING_GMAC_MIITX_04
In Table 7-72 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
288 Timing Requirements and Switching Characteristics
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