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| DRA722_17 Datasheet, PDF (290/408 Pages) Texas Instruments – Infotainment Applications Processor | |||
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DRA722, DRA724, DRA725, DRA726
SPRS956B â MARCH 2016 â REVISED JANUARY 2017
www.ti.com
No
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
PARAMETER
tc(MDC)
tw(MDCH)
tw(MDCL)
tsu(MDIO-MDC)
th(MDIO_MDC)
Table 7-73. Timing Requirements for MDIO Input
DESCRIPTION
MIN
Cycle time, MDC
400
Pulse Duration, MDC High
160
Pulse Duration, MDC Low
160
Setup time, MDIO valid before MDC High
90
Hold time, MDIO valid from MDC High
0
MAX
UNIT
ns
ns
ns
ns
ns
Table 7-74. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO
MDIO6
MDIO7
PARAMETER
tt(MDC)
td(MDC-MDIO)
DESCRIPTION
Transition time, MDC
Delay time, MDC High to MDIO valid
MIN
MAX
UNIT
5
ns
10
390
ns
MDCLK
MDIO
(input)
1
MDIO2
MDIO3
MDIO6
MDIO4
MDIO5
MDIO6
MDIO
(output)
MDIO7
Figure 7-57. GMAC MDIO diagrams
SPRS906_TIMING_GMAC_MDIO_05
In Table 7-75 are presented the specific groupings of signals (IOSET) for use with GMAC MDIO signals.
SIGNALS
mdio_d
mdio_mclk
Table 7-75. GMAC MDIO IOSETs
IOSET7
BALL
MUX
F6
3
D3
3
IOSET8
BALL
MUX
U4
0
V1
0
IOSET9
BALL
MUX
AB4
1
AC5
1
IOSET10
BALL
MUX
B20
5
B21
5
7.23.3 GMAC RMII Timings
The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from
PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the
device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the
PRCM chapter of the device TRM for full details about RMII reference clock.
290 Timing Requirements and Switching Characteristics
Copyright © 2016â2017, Texas Instruments Incorporated
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Product Folder Links: DRA722 DRA724 DRA725 DRA726
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