DRA722_17 Datasheet, PDF (393/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
DDR Address and Control Input Buffers
Processor
Address and Control
Output Buffer
Address and Control
Terminator
Rtt
A1
A2
AT
Vtt
SPRS906_PCB_DDR3_19
Figure 8-58. ADDR_CTRL Topology for One DDR3 Device
8.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
Figure 8-59 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-60
shows the corresponding ADDR_CTRL routing.
DDR_1V5
Rcp
Cac
A2
AT
A2
AT
Rcp
0.1 µF
=
SPRS906_PCB_DDR3_20
Figure 8-59. CK Routing for One DDR3 Device
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Applications, Implementation, and Layout 393
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