DRA722_17 Datasheet, PDF (304/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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SDR122
SDR121
SDR120
mmc1_clk
SDR123
mmc1_cmd
SDR124
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_06
Figure 7-68. MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode
7.25.1.4 SDR25, 4-bit data, half-cycle
Table 7-102 and Table 7-103 present Timing requirements and Switching characteristics for MMC1 -
SDR25 in receiver and transmitter mode (see Figure 7-69 and Figure 7-70).
Table 7-102. Timing Requirements for MMC1 - SD Card SDR25 Mode
NO. PARAMETER
SDR25 t_{su(cmdV-clkH)}
3
SDR25 t_h(clkH-cmdV)
4
SDR25 t_su(dV-clkH)
7
SDR25 t_h(clkH-dV)
8
DESCRIPTION
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
MODE
Pad Loopback Clock
Internal Loopback Clock
MIN
5.3
1.6
5.3
1.6
1.6
MAX UNIT
ns
ns
ns
ns
ns
Table 7-103. Switching Characteristics for MMC1 - SD Card SDR25 Mode
NO. PARAMETER
SDR251 fop(clk)
SDR252 t_w(clkH)
H
SDR252L t_w(clkL)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
Pulse duration, mmc1_clk low
SDR255 t_d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
SDR256 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185 ⁽¹⁾
-8.8
-8.8
MAX
48
6.6
6.6
UNIT
MHz
ns
ns
ns
ns
SDR251
SDR252L
SDR252H
mmc1_clk
SDR253
SDR254
mmc1_cmd
SDR257
SDR258
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_07
Figure 7-69. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
304 Timing Requirements and Switching Characteristics
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