 English |
|
|
|
|
|
|
|
| DRA722_17 Datasheet, PDF (118/408 Pages) Texas Instruments – Infotainment Applications Processor | |||
| |||
| ◁ |
DRA722, DRA724, DRA725, DRA726
SPRS956B â MARCH 2016 â REVISED JANUARY 2017
www.ti.com
Table 4-27. ATL Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
atl_clk2
Audio Tracking Logic Clock 2
atl_clk3
Audio Tracking Logic Clock 3
TYPE
O
O
4.4.25 Test Interfaces
BALL
B26
C23
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in Table 7-145.
NOTE
For more information, see the On-Chip Debug Support / Debug Ports section of the device
TRM.
SIGNAL NAME
tms
tdi
tdo
tclk
trstn
rtck
emu0
emu1
emu2
emu3
emu4
emu5
emu6
emu7
emu8
emu9
emu10
emu11
emu12
emu13
emu14
emu15
emu16
emu17
emu18
emu19
Table 4-28. Debug Signal Descriptions
DESCRIPTION
JTAG test port mode select. An external pullup resistor should be used on this
ball.
JTAG test data
JTAG test port data
JTAG test clock
JTAG test reset
JTAG return clock
Emulator pin 0
Emulator pin 1
Emulator pin 2
Emulator pin 3
Emulator pin 4
Emulator pin 5
Emulator pin 6
Emulator pin 7
Emulator pin 8
Emulator pin 9
Emulator pin 10
Emulator pin 11
Emulator pin 12
Emulator pin 13
Emulator pin 14
Emulator pin 15
Emulator pin 16
Emulator pin 17
Emulator pin 18
Emulator pin 19
TYPE
IO
I
O
I
I
O
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
BALL
F18
D23
F19
E20
D20
E18
G21
D24
F10
D7
A7
E1 / G11
G2 / E9
H7 / F9
G1 / F8
G6 / E7
F2 / D8
F3 / A5
D1 / C6
E2 / C8
D2 / C7
F4 / A8
C1 / C9
E4 / A9
F5 / B9
E6 / A10
118 Terminal Configuration and Functions
Copyright © 2016â2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese