DRA722_17 Datasheet, PDF (172/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
porz
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 5 Note 6
Note 8
Note 7
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vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3
vdd_dsp
vdd_gpu
vdd_iva
vdd_mpu
vdd, vdd_rtc⁽⁴⁾
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, vdda_core_gmac,
vdda_gpu, vdda_video, vdda_mpu,
vdda_osc, vdda_csi
vdds18v, vdds_mlbp, vdds18v_ddr1,
vdda_rtc⁽⁴⁾
xi_osc0
SPRS906_ELCH_05
Figure 5-5. Power-Down Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(4) If RTC-mode is not used then the following combinations are approved:
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
never higher than 2.0 V above the vdds18v rail.
172 Specifications
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