DRA722_17 Datasheet, PDF (266/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
(3) R = ACLKR/X period in ns.
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
ACLKR/X (CLKRP = CLKXP = 0) ^(A)
ACLKR/X (CLKRP = CLKXP = 1) ^(B)
AFSR/X (Bit Width, 0 Bit Delay)
4
3
4
6
5
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
8
7
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_01
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 7-41. McASP Input Timing
Table 7-49, Table 7-50, Table 7-51 and Figure 7-42 present Switching Characteristics Over
Recommended Operating Conditions for McASP1 to McASP8.
Table 7-49. Switching Characteristics Over Recommended Operating Conditions for McASP1⁽¹⁾
NO.
9
10
PARAMETER
t_c(AHCLKRX)
t_w(AHCLKRX)
11
t_c(ACLKRX)
DESCRIPTION
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
MODE
MIN
20
0.5P -
2.5 ⁽²⁾
20
MAX
UNIT
ns
ns
ns
266 Timing Requirements and Switching Characteristics
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