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| DRA722_17 Datasheet, PDF (328/408 Pages) Texas Instruments – Infotainment Applications Processor | |||
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DRA722, DRA724, DRA725, DRA726
SPRS956B â MARCH 2016 â REVISED JANUARY 2017
www.ti.com
7.29.2 Trace Port Interface Unit (TPIU)
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 7-145.
7.29.2.1 TPIU PLL DDR Mode
Table 7-144 and Figure 7-97 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
NO.
TPIU1
TPIU4
TPIU5
PARAMETER
tc(clk)
td(clk-ctlV)
td(clk-dataV)
Table 7-144. Switching Characteristics for TPIU
DESCRIPTION
Cycle time, TRACECLK period
Skew time, TRACECLK transition to TRACECTL transition
Skew time, TRACECLK transition to TRACEDATA[17:0]
MIN
5.56
-1.61
-1.61
MAX
1.98
1.98
UNIT
ns
ns
ns
TRACECLK
TRACECTL
TRACEDATA[X:0]
TPIU4
TPIU1
TPIU2
TPIU3
TPIU5
TPIU5
TPIU4
Figure 7-97. TPIU-PLL DDR Transmit Mode(1)
(1) In d[X:0], X is equal to 15 or 17.
SPRS906_TIMING_TIMER_01
In Table 7-145 are presented the specific groupings of signals (IOSET) for use with TPIU signals.
SIGNALS
emu19
emu18
emu17
emu16
emu15
emu14
emu13
emu12
emu11
emu10
emu9
emu8
emu7
emu6
BALL
E6
F5
E4
C1
F4
D2
E2
D1
F3
F2
G6
G1
H7
G2
Table 7-145. TPIU IOSETs
IOSET1
MUX
5
5
5
5
5
5
5
5
5
5
5
5
5
5
BALL
A10
B9
A9
C9
A8
C7
C8
C6
A5
D8
E7
F8
F9
E9
IOSET2
MUX
2
2
2
2
2
2
2
2
2
2
2
2
2
2
328 Timing Requirements and Switching Characteristics
Copyright © 2016â2017, Texas Instruments Incorporated
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Product Folder Links: DRA722 DRA724 DRA725 DRA726
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