DRA722_17 Datasheet, PDF (219/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 7-20 Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual
modes.
Table 7-20 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL
E21
F20
F21
B14
G13
J11
E12
F13
C12
D12
J14
E15
B15
A15
D15
B16
B17
BALL NAME
gpio6_14
gpio6_15
gpio6_16
mcasp1_aclkr
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_fsr
mcasp2_aclkr
mcasp2_axr0
mcasp2_axr1
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
Table 7-20. Manual Functions Mapping for DSS VOUT2 IOSET2
VOUT2_IOSET2_MANUAL1
A_DELAY (ps) G_DELAY (ps)
1983
0
2159
0
1864
0
2614
0
VOUT2_IOSET2_MANUAL2
A_DELAY (ps) G_DELAY (ps)
79
0
158
0
0
0
1255
0
VOUT2_IOSET2_MANUAL3
A_DELAY (ps) G_DELAY (ps)
68
0
148
0
0
0
1270
0
2705
0
1350
0
1360
0
2865
0
1210
0
1219
0
2759
0
1404
0
1413
0
2980
0
1325
0
1335
0
2634
0
1275
0
1289
0
2658
0
1302
0
1311
0
2818
0
1163
0
1172
0
2728
0
1373
0
1382
0
2513
0
319
534
308
560
2712
0
1357
0
1366
0
2529
0
1169
0
1184
0
2376
0
543
478
1029
0
2620
0
1265
0
1274
0
CFG REGISTER
CFG_GPIO6_14_OUT
CFG_GPIO6_15_OUT
CFG_GPIO6_16_OUT
CFG_MCASP1_ACLKR
_OUT
CFG_MCASP1_AXR2_
OUT
CFG_MCASP1_AXR3_
OUT
CFG_MCASP1_AXR4_
OUT
CFG_MCASP1_AXR5_
OUT
CFG_MCASP1_AXR6_
OUT
CFG_MCASP1_AXR7_
OUT
CFG_MCASP1_FSR_O
UT
CFG_MCASP2_ACLKR
_OUT
CFG_MCASP2_AXR0_
OUT
CFG_MCASP2_AXR1_
OUT
CFG_MCASP2_AXR4_
OUT
CFG_MCASP2_AXR5_
OUT
CFG_MCASP2_AXR6_
OUT
MUXMODE
6
vout2_hsync
vout2_vsync
vout2_fld
vout2_d0
vout2_d2
vout2_d3
vout2_d4
vout2_d5
vout2_d6
vout2_d7
vout2_d1
vout2_d8
vout2_d10
vout2_d11
vout2_d12
vout2_d13
vout2_d14
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Timing Requirements and Switching Characteristics 219