DRA722_17 Datasheet, PDF (365/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Item
Round pads
Vias
Table 8-11. USB1 Routing Recommendations (continued)
Description
Minimize pad size and round the corners of the pads for the ESD
and CMF components
Max 2 vias per signal trace. If vias are required, place vias close to
the AC Caps and CMFs. Vias under the SoC grid array may be used
if necessary to route signals away from BGA pattern.
Reason
Minimize capacitance
Vias significantly degrade signal
integrity at 2.5GHz
Figure 8-32 presents an example layout, demonstrating the “carve GND” concept.
AC Cap
AC Cap
CMF
CMF
Top Layer: Routing from SoC through
AC Caps, CMF, and ESD to connector.
Layer2, GND: Gaps carved in GND underneath
AC Caps, CMF, ESD, and connector.
Layer3, Signal: Implement as keep-out
zone underneath carved GND areas.
Layer4, GND Plane underneath AC Caps,
CMF, ESD, and connector.
Figure 8-32. USB 3.0 Example “carve GND” layout
SPRS85x_PCB_USB30_3
8.5.4 HDMI Board Design and Layout Guidelines
This section provides the timing specification for the HDMI interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface
requirements are met. The design rules stated within this document are targeted at resolutions less than
or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization.
8.5.4.1 HDMI Interface Schematic
The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return
Channel are not specifically supported by this Device):
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 365
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